1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly to a semiconductor device which provides for suppression of variation in characteristics among transistors by utilizing an offset spacer and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
In a semiconductor device, characteristics of a transistor depends on a configuration of a gate electrode. For this reason, variation in configuration among gate electrodes due to variation in density of gate electrodes in a gate electrode pattern within a wafer surface affects characteristics of transistors, resulting in variation in characteristics among the transistors. To overcome this drawback, Japanese Patent Application Laid-Open No. 8-204184 (pp. 3-4 and FIGS. 1 to 3, hereinafter referred to as “JP 8-204184”) has proposed a semiconductor device which is capable of obtaining uniform characteristics of transistors in a wafer surface in spite of variation in density of gate electrodes in a gate electrode pattern, as well as a method of manufacturing such a semiconductor device.
According to JP 8-204184, first, downwardly tapered gate electrodes are formed on a semiconductor substrate, each with a gate insulating film interposed therebetween. Impurities for forming lightly-doped diffusion layers are implanted into the semiconductor substrate using the gate electrodes as a mask. A sidewall is formed on a side face of each of the gate electrodes. Implants for forming another diffusion layers are implanted into the semiconductor substrate using the gate electrodes and the sidewalls collectively as a mask, to form sources/drains including the lightly-doped diffusion layers and the subsequently-formed diffusion layers, thereby to complete a semiconductor device. In this manner, it is possible to form the sidewalls uniform in width extending along a gate length on a bottom surface thereof.
As an alternative, a semiconductor device utilizing an offset spacer is shown in Japanese Patent Application Laid-Open No. 2002-289841 (pp. 6-8 and FIGS. 1 to 3, hereinafter referred to as “JP 2002-289841”). According to JP 2002-289841, a film of silicon oxide is formed on a semiconductor substrate, and a polysilicon film is formed thereon. Nitrogen is introduced into the polysilicon film in such a manner that an upper portion of the polysilicon film is doped more heavily than a lower portion. Thereafter, the polysilicon film is patterned to form gate electrodes. Another film of silicon oxide is formed so as to cover the gate electrodes, and then is locally removed, to form an offset spacer on a side face of each of the gate electrodes. The offset spacer is formed such that an upper portion thereof has a width smaller than a lower portion. Then, extension regions are formed in the semiconductor substrate, and a silicide film is formed in an upper portion of each of the gate electrodes.
JP 8-204184 is limited to a semiconductor device with a downwardly tapered gate electrode, and thus is not applicable to a semiconductor device with a gate electrode having a different configuration such as an upwardly tapered gate electrode or a gate electrode having a rectangular section. On the other hand, in JP 2002-289841, the offset spacers must be formed so as to comply with respective configurations of the gate electrodes because the offset spacers are formed by oxidation after a patterning process for forming the gate electrodes. This may possibly cause non-uniformity in characteristics among transistors within one wafer surface.